An Improved Two-Step Binary Logarithmic Converter for FPGAs
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/7094329/06998832.pdf?arnumber=6998832
Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications;Applied Sciences;2024-02-12
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3. Design and Circuit Implementation of Area-Delay-Product-Efficient Logarithmic Converters Using Mantissa-Bit Compensation Scheme;Circuits, Systems, and Signal Processing;2022-06-23
4. Half-Precision Logarithmic Arithmetic Unit Based on the Fused Logarithmic and Antilogarithmic Converter;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-02
5. Utilize the shift‐and‐add architecture to approximate multiple nonlinear functions;International Journal of Circuit Theory and Applications;2021-03-16
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