A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9016282/08723133.pdf?arnumber=8723133
Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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2. An Investigative Study on Performance and Reliability Effects on S2C/TSPC/SCD D-Flip-Flops using 16 nm CMOS Process;2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI);2024-03-14
3. High speed ultra-low-lower lulse-triggered JLFET Flip-Flop;Modern Physics Letters B;2023-10-19
4. A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18
5. Simple and Accurate Model for the Propagation Delay in MCML Gates;Electronics;2023-06-15
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