A Partially Static High Frequency 18T Hybrid Topological Flip-Flop Design for Low Power Application
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/4358609/09524743.pdf?arnumber=9524743
Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design and Analysis of Low-Power and Area-Efficient Master-Slave Flip-Flop;IETE Journal of Research;2024-05-21
2. An Investigative Study on Performance and Reliability Effects on S2C/TSPC/SCD D-Flip-Flops using 16 nm CMOS Process;2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI);2024-03-14
3. DNN-Based Optimization to Significantly Speed Up and Increase the Accuracy of Electronic Circuit Design;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-03
4. Yield Maximization of Flip-Flop Circuits Based on Deep Neural Network and Polyhedral Estimation of Nonlinear Constraints;IEEE Access;2024
5. Review of Dual-Edge Triggered Low-Power D Flip-Flops;2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2023-12-29
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