An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN-Reference-Cited by-同舟云学术

An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN

Published:2022-04 Issue:4 Volume:69 Page:2311-2315
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Kushwaha Dinesh¹^ORCID,Joshi Ashish²^ORCID,Kumar Chaudhry Indra³^ORCID,Gupta Neha¹^ORCID,Miryala Sandeep⁴^ORCID,Joshi Rajiv V.⁵,Dasgupta Sudeb¹,Bulusu Anand¹^ORCID

Affiliation:

1. Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India

2. IP Engineering Group’s (IPG), Intel Technology India Pvt. Ltd., Bengaluru, India

3. Department of Electrical Engineering, Delhi Technological University, New Delhi, India

4. Instrumentation Division, Brookhaven National Laboratory, Upton, NY, USA

5. Thomas J. Watson Research Center, Yorktown Heights, NY, USA

Funder

Semiconductor Research Corporation (SRC), India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9741739/09707498.pdf?arnumber=9707498

Reference17 articles.

1. 15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

2. 24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

3. 24.4 Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation

4. XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping

5. In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array

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