PAM-4/6/8 Performance and Power Analysis for Next Generation 224Gbit/s Links
Author:
Affiliation:
1. TU Berlin, FG Mixed Signal Circuit Design, Einsteinufer 17,Berlin,10587
2. Meta Inc., 1 Hacker Way,Menlo Park,CA,94025
3. Exsilica Corp., 680 Forest Ave,Palo Alto,CA,94301
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937895.pdf?arnumber=9937895
Reference12 articles.
1. 6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET
2. 6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET
3. An UWB 18.5 GS/s Sampling Front-End for a 74 GS/s 5-bit ADC in 22nm FDSOI
4. A 44fs RMS Jitter 6GHz Limiting Amplifier in 22nm CMOS FDSOI
5. Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX®
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1. Multi-Level Pattern Synthesis Based on FPGA and DAC;2023 IEEE 16th International Conference on Electronic Measurement & Instruments (ICEMI);2023-08-09
2. Design and verification of DFE re-decision algorithm for PAM6 high-speed transceiver based on FPGA;Journal of Instrumentation;2023-08-01
3. A 224 Gbit/s Transceiver Front-end Design for Next Generation Data Centers;2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2022-10-24
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