Multi-Level Pattern Synthesis Based on FPGA and DAC
Author:
Affiliation:
1. School of Automation Engineering, University of Electronic Science and Technology of China,Chengdu,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10269800/10269827/10270199.pdf?arnumber=10270199
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4. PAM-4/6/8 Performance and Power Analysis for Next Generation 224Gbit/s Links
5. Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies
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