A Novel Low-Leakage ESD Power Clamp Circuit with Adjustable Transient Response Time
Author:
Affiliation:
1. Peking University,Key Laboratory of Microelectronic Devices and Circuits (MoE), School of Integrated Circuis,Beijing,China,100871
2. Beijing Microelectronics Technology Institute,Beijing,China,100076
Funder
National Natural Science Foundation of China
State Grid Corporation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937535.pdf?arnumber=9937535
Reference13 articles.
1. Whole-chip ESD protection design with efficient VDD-to- VSS ESD clamp circuits for submicron CMOS VLSI;ker;IEEE Trans Electron Devices,1999
2. A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology
3. An Area-Efficient Clamp Based on Transmission Gate Feedback Technology for Power Rail Electrostatic Discharge Protection
4. Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
5. An on-chip combo clamp for surge and universal ESD protection in bulk FinFET technology
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1. Resistor-less power-rail ESD clamp circuit design with adjustable NMOS gate biased voltage;Semiconductor Science and Technology;2023-10-18
2. A False Trigger-Strengthened and Area-Saving Power-Rail Clamp Circuit with High ESD Performance;Micromachines;2023-05-31
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