A False Trigger-Strengthened and Area-Saving Power-Rail Clamp Circuit with High ESD Performance
-
Published:2023-05-31
Issue:6
Volume:14
Page:1172
-
ISSN:2072-666X
-
Container-title:Micromachines
-
language:en
-
Short-container-title:Micromachines
Author:
Ma Boyang1ORCID, Chen Shupeng1, Wang Shulong1ORCID, Qian Lingli2, Han Zeen1, Huang Wei1, Fu Xiaojun3, Liu Hongxia1ORCID
Affiliation:
1. Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices of Education, The School of Microelectronics, Xidian University, Xi’an 710071, China 2. Chongqing Acoustic-Optic-Electronic Co., Ltd. of CETC & 24 Institute, Chongqing 401331, China 3. National Key Laboratory of Integrated Circuits and Microsystems, Chongqing 401332, China
Abstract
A power clamp circuit, which has good immunity to false trigger under fast power-on conditions with a 20 ns rising edge, is proposed in this paper. The proposed circuit has a separate detection component and an on-time control component which enable it to distinguish between electrostatic discharge (ESD) events and fast power-on events. As opposed to other on-time control techniques, instead of large resistors or capacitors, which can cause a large occupation of the layout area, we use a capacitive voltage-biased p-channel MOSFET in the on-time control part of the proposed circuit. The capacitive voltage-biased p-channel MOSFET is in the saturation region after the ESD event is detected, which can serve as a large equivalent resistance (~106 Ω) in the structure. The proposed power clamp circuit offers several advantages compared to the traditional circuit, such as having at least 70% area savings in the trigger circuit area (30% area savings in the whole circuit area), supporting a power supply ramp time as fast as 20 ns, dissipating the ESD energy more cleanly with little residual charge, and recovering faster from false triggers. The rail clamp circuit also offers robust performance in an industry-standard PVT (process, voltage, and temperature) space and has been verified by the simulation results. Showing good performance of human body model (HBM) endurance and high immunity to false trigger, the proposed power clamp circuit has great potential for application in ESD protection.
Funder
Open Foundation of National Key Laboratory of Integrated Circuits and Microsystems Chongqing Acoustic-optic-electronic Co.Ltd. of CETC & 24 Institute Project National Natural Science Foundation of China
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
Reference21 articles.
1. Mergens, M., Wybo, G., Van Camp, B., Keppens, B., De Ranter, F., Verhaege, K., Jozwiak, P., Armer, J., and Russ, C. (2005, January 23–26). ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90 nm CMOS technolo-gies. Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, Kobe, Japan. 2. Duvvury, C. (2008, January 15–17). ESD qualification changes for 45nm and beyond. Proceedings of the 2008 IEEE International Electron Devices Meeting, San Francisco, CA, USA. 3. Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI;Ker;IEEE Trans. Electron Devices,1999 4. Karalkar, S.P., Ganesan, V., Paul, M., Hwang, K., and Gauthier, R. (2021, January 21–24). Design Optimization of MV-NMOS to Improve Holding Voltage of a 28 nm CMOS Technology ESD Power Clamp. Proceedings of the 2021 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA. 5. Li, C., Zhang, F., Wang, C., Qi, C., Lu, F., Wang, H., Di, M., Cheng, Y., Zhao, H., and Wang, A. (November, January 31). Temperature Dependence of Diode and ggNMOS ESD Protection Structures in 28 nm CMOS. Proceedings of the 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Qingdao, China.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
|
|