Resistor-less power-rail ESD clamp circuit design with adjustable NMOS gate biased voltage

Abstract

Abstract Based on the 0.18 μm CMOS process, proposed a new power-rail electrostatic discharge clamp circuit. The proposed circuit can adjust the voltage biased to the big clamp NMOS (Mbig) gate by adjusting the width of one MOS transistor, and the feedback path is designed to prolong the response time of Mbig. The simulation results demonstrated that the voltage biased to the Mbig of the proposed circuit has a relatively steady state and the Mbig has a longer response time, which can effectively reduce the damage to the gate oxide layer of the Mbig with large voltage overshoot. The transmission line pulse test results show that compared to the Mbig of the conventional circuit, the Mbig of the proposed circuit has higher trigger voltage, lower on-resistance, and better robustness.