A 5.0-to-12.5-Gb/s, 1.7-pJ/b, 0.66-μs Lock-time Reference-less Sub-sampling CDR with Beat Detection FLL in 28nm CMOS
Author:
Affiliation:
1. Sungkyunkwan University,Suwon,South Korea
2. Samsung Electronics,Hwaseong,South Korea
Funder
Samsung
IC Design Education Center
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9980472/9980536/09980827.pdf?arnumber=9980827
Reference5 articles.
1. A 6.5–12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS
2. A 6.7-11.2Gb/s, 2.25pJ/bit, Single-Loop Referencelesss CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS;park;JSSC,2018
3. 6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS
4. A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique
5. An Inductorless 20-Gb/s CDR With High Jitter Tolerance
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