A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/8476980/8494227/08494234.pdf?arnumber=8494234
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Low Power Injection-Locked CDR Using 28 nm FDSOI Technology for Burst-Mode Applications;Journal of Low Power Electronics and Applications;2024-04-07
2. Means to Accelerate Transfer of Information Between Integrated Circuits;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31
3. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07
4. New design of an ultra low power CDR architecture using FDSOI 28 nm technology;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26
5. A 6.0–11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-02
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