New design of an ultra low power CDR architecture using FDSOI 28 nm technology
Author:
Affiliation:
1. Université Côte d’Azur,Polytech’Lab, UPR UCA,Sophia Antipolis,France,7498
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10198027/10198028/10198143.pdf?arnumber=10198143
Reference15 articles.
1. A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology
2. Switching energy efficiency optimization for advanced CPU thanks to UTBB technology
3. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS
4. A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique
5. Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology
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