A 64-channel back-gate adapted ultra-low-voltage spike-aware neural recording front-end with on-chip lossless/near-lossless compression engine and 3.3V stimulator in 22nm FDSOI
Author:
Affiliation:
1. TU Dresden,Faculty of Electrical and Computer Engineering
Funder
European Regional Development Fund
Ministry of Education
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9980472/9980536/09980793.pdf?arnumber=9980793
Reference10 articles.
1. An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology
2. A 16384-electrode 1024-channel multimodal CMOS MEA for high-throughput intracellular action potential measurements and impedance spectroscopy in drug-screening applications
3. Intracellular Features Predicted by Extracellular Recordings in the Hippocampus In Vivo
4. A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI
5. Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology
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1. An 112-Ch Neural Signal Acquisition SoC With Full-Channel Read-Out and Processing Accelerators;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08
2. A 16-channel Real-time Adaptive Neural Signal Compression Engine in 22nm FDSOI;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26
3. A 3.3V Saturation-Aware Neurostimulator with Reset Functionality in 22 nm FDSOI;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26
4. Power Minimization in Neural Recording ΔΣ Modulators by Adaptive Back-Gate Voltage Tuning;IEEE Solid-State Circuits Letters;2023
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