An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors-Reference-Cited by-同舟云学术

An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors

Published:2023-01-01 Issue:1 Volume:72 Page:222-235
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Fadiheh Mohammad Rahmani¹^ORCID,Wezel Alex¹^ORCID,Muller Johannes¹,Bormann Jorg²,Ray Sayak³,Fung Jason M.³^ORCID,Mitra Subhasish⁴^ORCID,Stoffel Dominik¹^ORCID,Kunz Wolfgang¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Technische Universität Kaiserslautern, Kaiserslautern, Germany

2. Siemens EDA, München, Germany

3. Intel Product Assurance and Security, Intel Corporation, Portland, OR, USA

4. Department of Electrical and Computer Engineering, Department of Computer Science, Stanford University, Stanford, CA, USA

Funder

DFG SPP Nano Security

BMBF ZuSE Scale4Edge

Intel Corporation Side Channel Academic Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx7/12/9984045/09716812.pdf?arnumber=9716812

Reference44 articles.

1. Structural FSM Traversal

2. Verification of large synthesized designs

3. Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants

4. Symbolic Model Checking without BDDs

5. A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level

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