Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL
Author:
Affiliation:
1. RPTU Kaiserslautern-Landau,Germany
2. Stanford University,USA
3. Intel Corporation,USA
4. University of Illinois Urbana-Champaign,USA
Funder
Intel Corp.
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10323590/10323543/10323843.pdf?arnumber=10323843
Reference42 articles.
1. InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy
2. Path Predicate Abstraction for Sound System-Level Models of RT-Level Circuit Designs
3. Context-Sensitive Fencing
4. FLUSH+RELOAD: A High Resolution, Low Noise, L3 Cache Side-Channel Attack;yarom;23rd USENIX Security Symposium,2014
5. Efficient invisible speculative execution through selective delay and value prediction
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