SEIF: Augmented Symbolic Execution for Information Flow in Hardware Designs-Reference-Cited by-同舟云学术

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SEIF: Augmented Symbolic Execution for Information Flow in Hardware Designs

Published:2023-10-29 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 12th International Workshop on Hardware and Architectural Support for Security and Privacy
language:
Short-container-title:

Author:

Ryan Kaki¹^ORCID,Gregoire Matthew¹^ORCID,Sturton Cynthia¹^ORCID

Affiliation:

1. UNC Chapel Hill, USA

Funder

NSF (National Science Foundation)

Meta

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3623652.3623666

Reference60 articles.

1. [n. d.]. Cadence Verification. https://www.cadence.com/en_US/home/tools/system-design-and-verification.html [n. d.]. Cadence Verification. https://www.cadence.com/en_US/home/tools/system-design-and-verification.html

2. [n. d.]. openMSP430. https://opencores.org/projects/openmsp430 [n. d.]. openMSP430. https://opencores.org/projects/openmsp430

3. [n. d.]. OpenRISC 1200 Implementation. https://github.com/openrisc/or1200 [n. d.]. OpenRISC 1200 Implementation. https://github.com/openrisc/or1200

4. Clepsydra: Modeling timing flows in hardware designs

5. Register transfer level information flow tracking for provably secure hardware design

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