SOT-MRAM Digital PIM Architecture With Extended Parallelism in Matrix Multiplication
Author:
Affiliation:
1. School of Electrical Engineering, Korea University, Seoul, Korea
2. Department of Materials Science and Engineering, KAIST, Daejeon, Korea
3. Department of Physics, KAIST, Daejeon, Korea
Funder
Samsung
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software
Link
http://xplorestaging.ieee.org/ielx7/12/9913765/09729451.pdf?arnumber=9729451
Reference28 articles.
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4. Stateful Reconfigurable Logic via a Single-Voltage-Gated Spin Hall-Effect Driven Magnetic Tunnel Junction in a Spintronic Memory
5. Complementary logic operation based on electric-field controlled spin–orbit torques
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