Design and Analysis of Power and Area Efficient 4–2 Compressor Circuit for Tree Multiplier
Author:
Affiliation:
1. RV College of Engineering,Dept of ETE,Bengaluru,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10333972/10333315/10334133.pdf?arnumber=10334133
Reference16 articles.
1. Performance Analysis Comparison of 4-2 Compressors in 180nm CMOS Technology
2. Design of Low Power Reduced Complexity Wallace Tree Multiplier Using Positive Feedback Adiabatic Logic
3. Low Power Square Root Carry Select Adder using AVLS-TSPC-based D Flip-flop;Premananda;Electrica Journal,2022
4. Low-Power Phase Frequency Detector Using Hybrid AVLS and LECTOR Techniques for Low-Power PLL;Belegehalli;Advances in Electrical and Electronic Engineering, AEEE, Theoretical and Applied Electrical Engineering,2022
5. Design and performance analysis of modified unsigned braun and signed Baugh-Wooley multiplier
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