Design of Low Power Reduced Complexity Wallace Tree Multiplier Using Positive Feedback Adiabatic Logic

Author:

Ganavi M. G.,Premananda B. S.

Publisher

Springer Singapore

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and Analysis of Power and Area Efficient 4–2 Compressor Circuit for Tree Multiplier;2023 7th International Conference on Computation System and Information Technology for Sustainable Solutions (CSITSS);2023-11-02

2. Design and Analysis of CNTFET based Dynamic Comparator;2023 4th International Conference on Electronics and Sustainable Communication Systems (ICESC);2023-07-06

3. An Efficient Design and Performance Analysis of Novel 8 Bit Modified Wallace Multiplier Using Sklansky Adder in Comparison with Kogge-Stone Adder (KSA);2023 Eighth International Conference on Science Technology Engineering and Mathematics (ICONSTEM);2023-04-06

4. A Variant of Long Multiplication Design with Low Power and Area Using Modified 7:3 Compressor for Biomedical Applications;Wireless Personal Communications;2022-07-01

5. RDO-WT: optimised Wallace Tree multiplier based FIR filter for signal processing applications;International Journal of Electronics;2021-11-28

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