Author:
Biradar Vinay B.,Vishwas P. G.,Chetan C. S.,Premananda B. S.
Cited by
9 articles.
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1. LUT-Based Area-Optimized Accurate Multiplier Design for Signal Processing Applications;Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering;2024
2. A Serial-Parallel-Based 4-Bit Novel Multiplier: Design, Implementation, and Performance Analysis;2023 IEEE Silchar Subsection Conference (SILCON);2023-11-03
3. Design and Analysis of Power and Area Efficient 4–2 Compressor Circuit for Tree Multiplier;2023 7th International Conference on Computation System and Information Technology for Sustainable Solutions (CSITSS);2023-11-02
4. Efficient Multiplication and Accumulation of Signed Numbers;2022 IEEE International Symposium on Smart Electronic Systems (iSES);2022-12
5. RTL to GDSII Flow Implementation of 8-bit Baugh-Wooley Multiplier;2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO);2022-04-28