In-Depth DTCO Analysis on Scaling Gate-All-Around Nanosheets/Nanowires for 20 Å Node and Beyond Technologies-Reference-Cited by-同舟云学术

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In-Depth DTCO Analysis on Scaling Gate-All-Around Nanosheets/Nanowires for 20 Å Node and Beyond Technologies

Published:2024-08 Issue:8 Volume:71 Page:4483-4488
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Das Uttam Kumar¹^ORCID,Raza Ansari Md Hasan¹^ORCID,Hussain Muhammad Mustafa²^ORCID,El-Atab Nazek¹^ORCID

Affiliation:

1. Program of Electrical and Computer Engineering (ECE), Computer Electrical Mathematical Science and Engineering Division, King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia

2. Elmore Family School of Electrical and Computer Engineering (ECE), Purdue University, West Lafayette, IN, USA

Funder

Generous Baseline Fund of KAUST

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/16/10609410/10562352.pdf?arnumber=10562352

Reference27 articles.

1. High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

2. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

3. 3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology

4. Enabling next generation CMOS by novel EOT scaling module;Dong

5. Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

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