3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology

Author:

Song Taejoong1,Jung Hakchul1,Yang Giyoung1,Tang Hoyoung1,Kim Hayoung1,Seo Dongwook1,Kim Hoonki1,Rim Woojin1,Baek Sanghoon1,Baeck Sangyeop1,Jung Jonghoon1

Affiliation:

1. Samsung Electronics,Hwaseong,Korea

Publisher

IEEE

Reference11 articles.

1. Design Technology Co-Optimization in Technology Definition for 22nm and Beyond;northrop;Symp VLSI Technol Dig Tech Papers,0

2. The past present and future of design-technology co-optimization

3. 24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit

4. Pin Accessibility-Driven cell Layout Design and Placement Optimization;seo;ACM/EDAC/IEEE 54th Design Automation Conference (DAC),0

5. 15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. In-Depth DTCO Analysis on Scaling Gate-All-Around Nanosheets/Nanowires for 20 Å Node and Beyond Technologies;IEEE Transactions on Electron Devices;2024-08

2. 3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA’s 0.7V Thin-Gate-Oxide Transistor;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

3. Redefining Innovation: A Journey forward in New Dimension Era;2023 International Electron Devices Meeting (IEDM);2023-12-09

4. Multi-Source Transfer Learning for Design Technology Co-Optimization;2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED);2023-08-07

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