Latchup Risk in a 4H-SiC Process
Author:
Affiliation:
1. Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
Funder
National Science and Technology Council (NSTC), Taiwan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/16/10508280/10466501.pdf?arnumber=10466501
Reference15 articles.
1. Design, Process, and Characterization of Complementary Metal–Oxide–Semiconductor Circuits and Six-Transistor Static Random-Access Memory in 4H-SiC
2. Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C
3. First Integration of 10-V CMOS Logic Circuit, 20-V Gate Driver, and 600-V VDMOSFET on a 4H-SiC Single Chip
4. Latchup in CMOS Technology
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