SOT-MRAM-Based Design for Energy-Efficient and Reliable Binary Neural Network Acceleration-Reference-Cited by-同舟云学术

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SOT-MRAM-Based Design for Energy-Efficient and Reliable Binary Neural Network Acceleration

Published:2024-09 Issue:9 Volume:71 Page:5367-5374
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Shaban Ahmed¹^ORCID,Gothalyan Shreshtha²^ORCID,Hou Tuo-Hung³^ORCID,Suri Manan¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Indian Institute of Technology Delhi, New Delhi, India

2. Department of Electrical Engineering and Computer Science (EECS-IGP), National Yang Ming Chiao Tung University, Hsinchu, Taiwan

3. Department of Electrical Engineering, Institute of Electronics, and the Industry Academia Innovation School, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

Funder

National Science and Technology Council, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/16/10645717/10628035.pdf?arnumber=10628035

Reference20 articles.

1. BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

2. XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

3. Dual-configuration in-memory computing bitcells using SiO_x RRAM for binary neural networks

4. Fully Binarized, Parallel, RRAM-Based Computing Primitive for In-Memory Similarity Search

5. Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction

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