Dual-configuration in-memory computing bitcells using SiO<sub><i>x</i></sub> RRAM for binary neural networks-Reference-Cited by-同舟云学术

Dual-configuration in-memory computing bitcells using SiO_x RRAM for binary neural networks

Published:2022-01-17 Issue:3 Volume:120 Page:034102
ISSN:0003-6951
Container-title:Applied Physics Letters
language:en
Short-container-title:Appl. Phys. Lett.

Author:

Kingra Sandeep Kaur¹^ORCID,Parmar Vivek¹^ORCID,Negi Shubham¹,Bricalli Alessandro²,Piccolboni Giuseppe²,Regev Amir²^ORCID,Nodin Jean-François³,Molas Gabriel³^ORCID,Suri Manan¹^ORCID

Affiliation:

1. Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India

2. Weebit Nano, Hod Hasharon, Israel

3. CEA-Leti, Grenoble, France

Funder

Science and Engineering Research Board

Indian Institute of Technology Delhi

Publisher

AIP Publishing

Subject

Physics and Astronomy (miscellaneous)

Link

https://aip.scitation.org/doi/pdf/10.1063/5.0073284

Reference11 articles.

1. H.T. Lue , P.K. Hsu , M.L. Wei , T.H. Yeh , P.Y. Du , W.C. Chen , K.C. Wang , and C.Y. Lu , in 2019 IEEE International Electron Devices Meeting (IEDM) ( IEEE, 2019), pp. 38.1.1–38.1.4.

2. W. H. Choi , P.F. Chiu , W. Ma , G. Hemink , T. T. Hoang , M. Lueker-Boden , and Z. Bandic , in 2020 IEEE International Symposium on Circuits and Systems (ISCAS) ( IEEE, 2020), pp. 1–5.

3. M. Bocquet , T. Hirztlin , J.O. Klein , E. Nowak , E. Vianello , J.M. Portal , and D. Querlioz , in 2018 IEEE International Electron Devices Meeting (IEDM) ( IEEE, 2018), pp. 20.6.1–20.6.4.

4. Hardware implementation of RRAM based binarized neural networks

5. High-Throughput In-Memory Computing for Binary Deep Neural Networks With Monolithically Integrated RRAM and 90-nm CMOS

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Open-RIMC: Open-Source RRAM-based IMC Co-Processor with Reconfigurable Logic Mapping;2023 IEEE 23rd International Conference on Nanotechnology (NANO);2023-07-02

2. Demonstration of SMT-reflow Immune and SCA-resilient PUF on 28nm RRAM device array;2023 IEEE International Memory Workshop (IMW);2023-05

3. Analysis of VMM computation strategies to implement BNN applications on RRAM arrays;APL Machine Learning;2023-04-13

4. Super-steep synapses based on positive feedback devices for reliable binary neural networks;Applied Physics Letters;2023-03-06

5. Demonstration of Differential Mode Ferroelectric Field‐Effect Transistor Array‐Based in‐Memory Computing Macro for Realizing Multiprecision Mixed‐Signal Artificial Intelligence Accelerator;Advanced Intelligent Systems;2023-02-22