Affiliation:
1. Department of Electrical and Computer Engineering The University of Texas at Austin Austin Texas 78172 USA
2. Department of Electrical and Computer Engineering Sungkyunkwan University Suwon 16419 South Korea
3. Division of Materials Science and Engineering Hanyang University Seoul 04763 South Korea
Abstract
Abstract3D neuromorphic hardware system is first demonstrated in neuromorphic application as on‐chip level by integrating array devices with CMOS circuits after wafer bonding (WB) and interconnection process. The memory window of synaptic device is degraded after WB and 3 Dimesional (3D) integration due to process defects and thermal stress. To address this degradation, Ag diffusion in materials of Ta2O5 and HfO2 is studied in a volatile memristor, furthermore, the interconnection and gate metal Ru are investigated to reduce defective traps of gate interface in non‐volatile memory devices. As a result, a memory window is improved over 106 in both types of devices. Improved and 3D integrated 12 × 14 array devices are identified in the synaptic characteristics according to the change of the synaptic weight from the interconnected Test Element Group (TEG) of the Complementary Metal Oxide Semiconductor (CMOS) circuits. The trained array devices present recognizable image of letters, achieving an accuracy rate of 92% when utilizing a convolutional neural network, comparing the normalized accuracy of 93% achieved by an ideal synapse device. This study proposes to modulate the memory windows up to 106 in an integrated hardware‐based neural system, considering the possibility of device degradation in both volatile and non‐volatile memory devices demonstrated by the hardware neural system.
Funder
National Research Foundation of Korea
Reference54 articles.
1. T.Hirtzlin M.Bocquet M.Ernoult J.‐O.Klein E.Nowak E.Vianello J.‐M.Portal D.Querlioz 2019 IEEE International Electron Devices Meeting (IEDM) IEEE Piscataway NJ2019.
2. 1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks
3. H.Wang D.‐Y.Yeung 2019 IEEE Int. Electron Devices Meeting (IEDM) IEEE Piscataway NJ2019.
4. S.Bianchi I.Munoz‐Martin G.Pedretti O.Melnic S.Ambrogio D.Ielmini inDigest of Technical Papers – Symp. on VLSI Technology 2019 T172.
5. An RRAM retention prediction framework using a convolutional neural network based on relaxation behavior
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献