Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9060423/9073194/09073285.pdf?arnumber=9073285
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. SOT-MRAM-Based Design for Energy-Efficient and Reliable Binary Neural Network Acceleration;IEEE Transactions on Electron Devices;2024-09
2. Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network Hardware;IEICE Transactions on Information and Systems;2024-08-01
3. Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04
4. Open-RIMC: Open-Source RRAM-based IMC Co-Processor with Reconfigurable Logic Mapping;2023 IEEE 23rd International Conference on Nanotechnology (NANO);2023-07-02
5. Approximate computation based on NAND-SPIN MRAM for CNN on-chip training;Proceedings of the 17th ACM International Symposium on Nanoscale Architectures;2022-12-07
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