Author:
Shinde Jitesh,Salankar S. S.
Cited by
26 articles.
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1. Design and Implementation of Low Power Golay Encoder Architecture;2024 5th International Conference for Emerging Technology (INCET);2024-05-24
2. Impact of Clock-Gating on ALU Optimized RISC-V Microarchitectures for Low Power Applications;2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2024-05-17
3. Detection of Malicious Threats Exploiting Clock-Gating Hardware Using Machine Learning;Sensors;2024-02-02
4. An Efficient ALU Architecture Design for Low Power IoT Application;2024 International Conference on Advancements in Smart, Secure and Intelligent Computing (ASSIC);2024-01-27
5. Analysis of Clock Gating Techniques for Low Power;Lecture Notes in Electrical Engineering;2024