Author:
Alaghi Armin,Karimi Naghmeh,Sedghi Mahshid,Navabi Zainalabedin
Cited by
39 articles.
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1. Fault-Tolerant Network-On-Chip;Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design;2023
2. Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation;2019 32nd IEEE International System-on-Chip Conference (SOCC);2019-09
3. A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip;Journal of Electronic Testing;2019-04
4. Network adapter architectures in network on chip: comprehensive literature review;Cluster Computing;2019-03-15
5. Efficient Post-Silicon Validation of Network-on-Chip Using Wireless Links;2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID);2019-01