Efficient Post-Silicon Validation of Network-on-Chip Using Wireless Links
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8698529/8710751/08711261.pdf?arnumber=8711261
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Hybrid Optimized Verification Methodology using Deep Reinforcement Neural Network;Journal of Intelligent & Fuzzy Systems;2023-08-24
2. Network-on-Chip Trust Validation Using Security Assertions;Journal of Hardware and Systems Security;2022-12
3. Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-11
4. Efficient Hardware Verification Using Machine Learning Approach;2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS);2019-12
5. Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation;2019 32nd IEEE International System-on-Chip Conference (SOCC);2019-09
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