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Network-on-Chip Trust Validation Using Security Assertions

Published:2022-12 Issue:3-4 Volume:6 Page:79-94
ISSN:2509-3428
Container-title:Journal of Hardware and Systems Security
language:en
Short-container-title:J Hardw Syst Secur

Author:

Jayasena Aruna^ORCID,Kumar Binod,Charles Subodha,Witharana Hasini,Mishra Prabhat

Funder

Semiconductor Research Corporation

National Science Foundation

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Building and Construction

Link

https://link.springer.com/content/pdf/10.1007/s41635-022-00129-5.pdf

Reference42 articles.

1. Parikh R, Bertacco V (2014) Forever: A complementary formal and runtime verification approach to correct noc functionality. ACM Trans Embed Comput Syst 13(3s):104:1–104:30. https://doi.org/10.1145/2514871

2. Abdel-Khalek R, Parikh R, DeOrio A, Bertacco V (2011) Functional correctness for cmp interconnects. In: ICCD, pp 352–359. http://doi.org/10.1109/ICCD.2011.6081423

3. Arteris (2009) Flexnoc resilience package. http://arteris.com/flexnoc-resilience-package-functional-safety, [Online]

4. Foster H, Lacey D, Krolnik A (2003) Assertion-Based Design, 2nd edn. Kluwer Academic Publishers, USA

5. Tehranipoor M, Koushanfar F (2010) A survey of hardware trojan taxonomy and detection. IEEE Des Test Comput 27(1):10–25

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1. Verifying Memory Confidentiality and Integrity of Intel TDX Trusted Execution Environments;2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST);2024-05-06

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