Fault-Tolerant Core Mapping for NoC based architectures with improved Performance and Energy Efficiency
Author:
Affiliation:
1. School of Electronic Systems and Automation, Digital University Kerala (former IIITM-Kerala),India
2. VNR Vignana Jyothi College of Engineering and Technology,Department of ECE,Hyderabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9970762/9970770/09970825.pdf?arnumber=9970825
Reference16 articles.
1. System level fault-tolerance core mapping and FPGA-based verification of NoC;kumar;Microelectronics Journal,2017
2. Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips
3. Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips
4. An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC)
5. An adaptive core mapping algorithm on NoC for future heterogeneous system-on-chip
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