An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC)-Reference-Cited by-同舟云学术

An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC)

Published:2019 Issue: Volume: Page:631-640
ISSN:1865-0929
Container-title:Communications in Computer and Information Science
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Author:

Reddy B. Naresh Kumar,Sireesha

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-13-5950-7_52

Reference20 articles.

1. Benini, L., De Micheli, G.: Networks on chips: a new SoC paradigm. IEEE Comput. 35(1), 70–78 (2002)

2. DiTomaso, D., Morris, R., Kodi, A.K., Sarathy, A., Louri, A.: Extending the energy efficiency and performance with channel buffers, crossbars, and topology analysis for network on chips. IEEE Trans. Very Large Scale Integr. Syst. 21(11), 2141–2154 (2013)

3. Naresh Kumar Reddy, B., Vasantha, M.H., Nithin Kumar, Y.B., Sharma, D.: Communication energy constrained spare core on NoC. In: 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT), pp. 1–4 (2015)

4. Naresh Kumar Reddy, B., Vasantha, M.H., Nithin Kumar, Y.B., Sharma, D.: A fine grained position for modular core on NoC. In: IEEE International Conference on Computer, Communication and Control, pp. 1–4 (2015)

5. Koziris, N., Romesis, M., Tsanakas, P., Papakonstantinou, G.: An efficient algorithm for the physical mapping of clustered task graphs onto multiprocessor architectures. In: Proceedings 8th Euromicro Workshop on Parallel and Distributed Processing (2000)

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