Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching-Reference-Cited by-同舟云学术

Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching

Published:2023-01 Issue:1 Volume:22 Page:17-20
ISSN:1556-6056
Container-title:IEEE Computer Architecture Letters
language:
Short-container-title:IEEE Comput. Arch. Lett.

Author:

Jimenez Daniel A.¹^ORCID,Teran Elvira²^ORCID,Gratz Paul V.³^ORCID

Affiliation:

1. Department of Computer Science & Engineering, Texas A&M University, College Station, TX, USA

2. School of Engineering, Texas A&M International University, Laredo, TX, USA

3. Department of Electrical & Computer Engineering, Texas A&M University, College Station, TX, USA

Funder

National Science Foundation

Semiconductor Research Corporation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Hardware and Architecture

Link

https://ieeexplore.ieee.org/ielam/10208/10006348/10035944-aam.pdf

Reference24 articles.

1. Best-offset hardware prefetching

2. XSBench - the development and verification of a performance abstraction for Monte Carlo reactor analysis;tramm;Proc Conf Role React Phys Toward Sustain Future,2014

3. Effective Mimicry of Belady’s MIN Policy

4. The GAP benchmark suite;beamer,2015

5. Division of Labor: A More Effective Approach to Prefetching

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1. Exploration and optimization of novel replacement and prefetching strategies for inefficiencies of advanced MRAM-based hybrid cache systems;Semiconductor Science and Technology;2024-08-01

2. Genetic Improvement of Last Level Cache;Lecture Notes in Computer Science;2024

3. CABARRE: Request Response Arbitration for Shared Cache Management;ACM Transactions on Embedded Computing Systems;2023-09-09

4. Design of DMS-RRIP replacement algorithm for L1-cache of RISC-V-based single-core embedded processor;Second International Conference on Electronic Information Technology (EIT 2023);2023-08-15