Parasitic Capacitances: Analytical Models and Impact on Circuit-Level Performance-Reference-Cited by-同舟云学术

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Parasitic Capacitances: Analytical Models and Impact on Circuit-Level Performance

Published:2011-05 Issue:5 Volume:58 Page:1361-1370
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Lan Wei ,Boeuf Frédéric,Skotnicki T,Wong H.-S Philip

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/16/5753310/05741718.pdf?arnumber=5741718

Cited by 36 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-01

2. Parasitic Capacitance Model for Stacked Gate-All-Around Nanosheet FETs;IEEE Transactions on Electron Devices;2024-01

3. Contact engineering for organic CMOS circuits;Journal of Physics: Materials;2023-11-24

4. Analytical modeling of negative capacitance transistor based ultra low power Schmitt trigger;Solid-State Electronics;2023-09

5. Exploring FinFET and Gate-All-Around FET for SRAM Cell Arrays at the 3 nm Process Node;2023 IEEE International Opportunity Research Scholars Symposium (ORSS);2023-04-23

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