Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits-Reference-Cited by-同舟云学术

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Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits

Published:2010 Issue: Volume: Page:
ISSN:
Container-title:2010 40th IEEE International Symposium on Multiple-Valued Logic
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Author:

Datla Satyendra R.P. Raju,Thornton Mitchell A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5489040/5489109/05489237.pdf?arnumber=5489237

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of new low-power and high-speed quaternary flip-flops based on CNTFETs;Computers and Electrical Engineering;2024-07

2. Low-Power Bus Encoding by Ternary LWC and Quaternary Transition Signaling: From Initial Concept to Circuit Design;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023

3. Energy Efficient Tri-State CNFET Ternary Logic Gates;International Journal of Nanoscience;2022-08

4. High-performance quaternary latch and D-Type flip-flop with selective outputs;Microelectronics Journal;2021-07

5. Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors;ETRI Journal;2021-06-13

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