A XOR-tree based technique for constant testability of configurable FPGAs
Author:
Publisher
IEEE Comput. Soc
Link
http://xplorestaging.ieee.org/ielx3/5068/13856/00643966.pdf?arnumber=643966
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs;2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC);2022-01-17
2. Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-12
3. An Improvement Test Approach of Look-up Table in SRAM-Based FPGAs;Advanced Materials Research;2010-12
4. Full coverage location of logic resource faults in A SOC co-verification technology based FPGA functional test environment;2009 IEEE 8th International Conference on ASIC;2009-10
5. Area Minimization of Exclusive-OR Intensive Circuits in FPGAs;Journal of Electronic Testing;2004-12
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