An Improvement Test Approach of Look-up Table in SRAM-Based FPGAs

Abstract

This paper proposes an improvement test approach of Look-Up Table in SRAM-based FPGAs from the third-party testing. This approach solves the mismatch problem which happens in the process of synthesis. Meanwhile, it also eliminates the problem of waveform distortion and period error which are caused by the superposing of different addresses. Though the number of the partial chain increases, the modification for CUT structure will not increase the test time notable. More importantly, the modified approach can ensure the correctness of synthesis result. Besides, because the modified BIST for testing the Look-Up Table is achieved by using Hardware Description Languages, it has the characteristics on general-purpose employ and flexibility.