Six subthreshold full adder cells characterized in 90 nm CMOS technology-Reference-Cited by-同舟云学术

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Six subthreshold full adder cells characterized in 90 nm CMOS technology

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Container-title:2006 IEEE Design and Diagnostics of Electronic Circuits and systems
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Author:

Granhaug K.,Aunet S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/10974/34591/01649565.pdf?arnumber=1649565

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Implementation of an Adder Circuit for Minimal Power and Less Delay Systems;2023 International Conference on Circuit Power and Computing Technologies (ICCPCT);2023-08-10

2. A novel design of full adder cell for VLSI applications;International Journal of Electronics;2022-04-21

3. A Subthreshold Bootstrapped SAPTL-Based Adder Design;Electronics;2019-10-12

4. Fast low-power full-adders based on bridge style minority function and multiplexer for nanoscale;International Journal of Electronics;2013-06

5. High-speed full adder based on minority function and bridge style for nanoscale;Integration;2011-06

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