A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems-Reference-Cited by-同舟云学术

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A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems

Published:2023-11-05 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Author:

Ikeda Shinichi¹,Iwata Akira¹,Otomo Goichi¹,Suzuki Tomoaki¹,Iijima Hiroaki¹,Shiraishi Mikio¹,Kawakami Shinya¹,Eimitsu Masatomo¹,Matsuoka Yoshiki¹,Sato Kiyohito¹,Tsuchiya Shigehiro¹,Shigeta Yoshinori¹,Aoyama Takuma¹

Affiliation:

1. Kioxia Corporation,Yokohama,Japan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10347557/10347908/10348001.pdf?arnumber=10348001

Reference6 articles.

1. A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface

2. 13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs

3. A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage

4. Modeling Oscillator Injection Locking Using the Phase Domain Response

5. A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces

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