Investigation of Ge channel Complemental Field Effect Transistors (CFETs) Stacked Epitaxy or Layer Transfer
Author:
Affiliation:
1. National Yang Ming Chiao Tung University,Department of Electrophysics,Hsinchu,Taiwan
2. National Applied Research Laboratories,Taiwan Semiconductor Research Institute,Hsinchu,Taiwan
Funder
Ministry of Science and Technology
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9797886/9797892/09798293.pdf?arnumber=9798293
Reference8 articles.
1. Stacked Ge-Nanosheet GAAFETs Fabricated by Ge/Si Multilayer Epitaxy
2. Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters
3. Wet Alkaline Etching of Si Selectively to SiGe for sub 10 nm Gate All Around Architectures
4. Significant Performance Enhancement of UTB GeOI pMOSFETs by Advanced Channel Formation Technologies Threshold voltage control by substrate bias in 10-nm-diameter tri-gate nanowire MOSFET on ultrathin BOX;chang;IEEE VLSI,2018
5. First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Vertically Stacked Nanosheet Number Optimization Strategy for Complementary FET (CFET) Scaling Beyond 2 nm;IEEE Transactions on Electron Devices;2023-12
2. Nanosheet Count Optimization Strategy of Complementary FET (CFET) Scaling Beyond 2 nm From Device to Circuit;2023 International Workshop on Advanced Patterning Solutions (IWAPS);2023-10-26
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