SiGe and Si Gate-All-Around FET Fabricated by Selective Etching the Same Epitaxial Layers
Author:
Affiliation:
1. Taiwan Semiconductor Research Institute,NARL,Hsinchu,Taiwan
2. National Yang Ming Chiao Tung University,International College of Semiconductor Technology,Hsinchu,Taiwan
Funder
Ministry of Science and Technology
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9797886/9797892/09797991.pdf?arnumber=9797991
Reference11 articles.
1. Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High ION/IOFF Ratio
2. Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies
3. First Demonstration of 4-Stacked Ge0.915 Sn0.085 Wide Nanosheets by Highly Selective Isotropic Dry Etching with High S/D Doping and Undoped Channels;huang;IEEE Symposium on VLSI Technology,2020
4. A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices
5. Stacked Ge Nanosheet GAAFETs Fabrication and Strain Effects Measurement
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Si Multi-Bridge Channel CMOS Inverter with Five Stacked Layers Fabricated from Epitaxial Si0.8Ge0.2/Si Multilayers;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22
2. Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM;Journal of Semiconductors;2023-12-01
3. Si Interlayers Trimming Strategy in Gate-All-Around Device Architecture for Si and SiGe Dual-Channel CMOS Integration;IEEE Transactions on Electron Devices;2023-12
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