CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration
Author:
Affiliation:
1. Centro ALGORTIMI/LASI, Universidade do Minho, Braga, Portugal
2. Department of Electrical, Electronic and Information Technologies Engineering (DEI), University of Bologna, Bologna, Italy
Funder
Technology Innovation Institute
European PILOT
European Processor Initiative Specific Grant Agreement 2 (EPI SGA2)
Fundação para a Ciência e Tecnologia (FCT) through the Research and Development Units Project Scope
Scholarships Project Scope
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/10287007/10233226.pdf?arnumber=10233226
Reference49 articles.
1. Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training
2. Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
3. Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product
4. The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology
5. HULK-V: A heterogeneous ultra-low-power Linux capable RISC-V SOC;valente;arXiv 2211 14944,2022
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. “Interrupting” the Status Quo: A First Glance at the RISC-V Advanced Interrupt Architecture (AIA);IEEE Access;2024
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