Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product

Author:

Chen Chen,Xiang Xiaoyan,Liu Chang,Shang Yunhai,Guo Ren,Liu Dongqi,Lu Yimin,Hao Ziyi,Luo Jiahui,Chen Zhijian,Li Chunqiang,Pu Yu,Meng Jianyi,Yan Xiaolang,Xie Yuan,Qi Xiaoning

Publisher

IEEE

Cited by 61 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Ditching the Queue: Optimizing Coprocessor Utilization with Out-of-Order CPUs on Compact Systems on Chip;Electronics;2024-07-31

2. Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor;IEEE Transactions on Computers;2024-07

3. ReBEC: A replacement-based energy-efficient fault-tolerance design for associative caches;Future Generation Computer Systems;2024-06

4. Skip It: Take Control of Your Cache!;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2024-04-27

5. Serverless? RISC more!;Proceedings of the 2nd Workshop on SErverless Systems, Applications and MEthodologies;2024-04-22

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