Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training-Reference-Cited by-同舟云学术

Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training

Published:2022-09-19 Issue: Volume: Page:
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Container-title:ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)
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Author:

Garofalo Angelo¹,Perotti Matteo²,Valente Luca¹,Tortorella Yvan¹,Nadalini Alessandro¹,Benini Luca¹,Rossi Davide¹,Conti Francesco¹

Affiliation:

1. University of Bologna,Department of Electrical, Electronic and Information Engineering (DEI),Italy

2. ETH Zürich,Integrated Systems Laboratory (IIS),Switzerland

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9911257/9911222/09911384.pdf?arnumber=9911384

Reference16 articles.

1. Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode;ottavi;ArXiv Preprint,2022

2. SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode

3. FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing

4. Hybrid 8-bit floating point (HFP8) training and inference for deep neural networks;sun;Advances in neural information processing systems,0

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