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A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs

  • Published:2017-07 Issue:7 Volume:25 Page:2071-2080
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Reddy Raviteja P.,Acharyya AmitORCID,Khursheed Saqib

Funder

Defence Research and Development Organization Government of India

Ministry of Electronics and Information Technology Government of India through the Visvesvaraya Ph.D. Fellowship

Department of Electrical Engineering and Electronics University of Liverpool Liverpool L69 3BX U.K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 20 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Instant Test and Repair for TSVs using Differential Signaling;Journal of Electronic Testing;2024-04

2. TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-04

3. A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs;ACM Journal on Emerging Technologies in Computing Systems;2022-10-13

4. Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement;IEEE Design & Test;2022-10

5. TRUST: Through-Silicon Via Repair Using Switch Matrix Topology;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022
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