Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/8628286/08528559.pdf?arnumber=8528559
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A high constancy and noise suppression voltage shift generator in SEIR-based BIST circuit for ADC linearity test;Microelectronics Journal;2024-09
2. A stimulus identification method for high-resolution ADC linearity testing using low-precision ramp signals;IEICE Electronics Express;2024
3. Machine Learning Support for Diagnosis of Analog Circuits;Machine Learning Support for Fault Diagnosis of System-on-Chip;2022-10-22
4. Digital-to-Analog Hardware Trojan Attacks;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-02
5. High-speed CMOS ramp generator using proteretic comparator;2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS);2021-11-22
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