High-speed CMOS ramp generator using proteretic comparator
Author:
Affiliation:
1. Center for VLSI and Embedded Systems (CVEST), IIIT,Hyderabad,India
2. CVEST, IIIT,Hyderabad,India
3. Muffakhan Jah College of Engg and Tech,ECE Department,Hyderabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9687621/9687623/09687792.pdf?arnumber=9687792
Reference8 articles.
1. Ramp ADC Speed-up Techniques for CMOS Image Sensors with New Image Quality Metric
2. A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors
3. Clockwise hysteresis or proteresis
4. Implementation of a ramp generator with Schmitt trigger circuit for PWM modulator applications
5. CMOS Schmitt trigger design
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