A 12–14.5-GHz 10.2-mW −249-dB FoM Fractional-<i>N</i> Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS-Reference-Cited by-同舟云学术

A 12–14.5-GHz 10.2-mW −249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS

Published:2022-05 Issue:5 Volume:30 Page:634-643
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Chen Yan-Ting¹^ORCID,Peng Pen-Jui²^ORCID,Lin Hung-Wen¹

Affiliation:

1. Department of Electrical Engineering, Yuan Ze University, Taoyuan, Taiwan

2. Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan

Funder

Young Scholar Fellowship Program by the Ministry of Science and Technology (MOST), Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

Reference23 articles.

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A low in-band phase noise Fractional-N ADPLL based on Switched-Capacitor-DPI;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. A Wide-Range and High-Linearity Timing Generator with 1.25ps-Resolution;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

5. Design High Frequency Phase Locked Loop Using Single Ended VCO for High Speed Applications;2022 IEEE Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI);2022-12-21