A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs

Author:

Ahmadi MehrnazORCID,Salamat Sahand,Alizadeh BijanORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Low-Power Timing-Error-Tolerant Circuit by Controlling A Clock;2024 International Conference on Smart Systems for applications in Electrical Sciences (ICSSES);2024-05-03

2. TEPD: A Compound Timing Detection of Both Data-Transition and Path-Activation for Reliable In-Situ Timing Error Detection and Correction in 28nm CMOS;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05

3. High-Performance ADC Design Using Fast Prediction Logic with Dynamic Clock Stretching Mechanism;2023 International Conference on Sustainable Computing and Data Communication Systems (ICSCDS);2023-03-23

4. Static Timing Analysis of Multibit Flipflop based LFSR;2022 6th International Conference on Computation System and Information Technology for Sustainable Solutions (CSITSS);2022-12-21

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